1. Field of the Invention
The object of the invention relates to a frequency divider.
It relates especially to a multi-octave frequency divider with a structure known as a funnel structure and a synchronous output.
It can be applied in the field of frequency synthesis and more particularly in the field of phase-locked loop frequency synthesis.
It can also constitute a basic cell of a programmable digital component of the FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processing) type.
It can also be used for pulse generators with very low jitter.
2. Description of the Prior Art
FIG. 1 shows an exemplary prior art divider.
It is formed by a prescaler 1 that divides the input frequency Fe by Na or by Na+1, a first counter A, referenced 2, whose output TC controls the division of the prescaler by Na or by Na+1, a second counter B, referenced 3, whose output TC is the output of the divider.
The assembly works as follows: when the counter B reaches the end of the counting stage (which corresponds to the end of a frame), it delivers the signal TC which respectively reloads the two counters with the values A and B, in complying with B≧A. A new frame then starts. So long as the counter A has not finished counting, the prescaler 1 divides the input frequency Fe by Na+1. This means that whenever A and B are counted down by one unit, the prescaler 1 counts (Na+1) cycles of the input signal with a period Te. The counter A therefore reaches the end of counting at the end of A*(Na+1) cycles with a duration Te. At this point in time, the counter A stops and orders the prescaler to perform a division by Na. To reach the end of counting, the counter B must again count B−A, which corresponds to Na*(B−A) cycles of the input signal. The device then returns to the initial state.
The total number of cycles of the input signal during a frame gives the division rank N of the divider:N=A(Na+1)+Na(B−A)N=A+BNa
So that N may evolve continuously in steps of 1, A should be programmable between 0 and Na−1. Since B is greater than or equal to A, we have Bmin=Na−1.
Hence Mmin=Na*(Na−1).
For a ⅘ prescaler, the minimum division rank needed to obtain continuity in steps of 1 is therefore equal to 12.
A structure of this kind has especially the following drawbacks:
The counters A and B are synchronous counters for which all the stages must work at a high frequency equal to Fe/Na,
For a division rank N varying from a few units to several hundreds of units, these synchronous counters give rise to very high consumption (given a high operating frequency and a large number of stages),
It is not easy to implement the fractional modes,
The number of logic layers between the input and the output is generally greater, thus limiting the phase noise performance.